Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, retaining its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
EEPROM and electrically programmable read-only memory (EPROM) are non-volatile memory that can be erased and have new data written or “programmed” into their memory cells.
An EPROM utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charge and therefore an EPROM memory cell can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
For EPROM memory, the transistor serving as a memory cell is typically programmed to a programmed state by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory is bulk erasable by removing the charge on the floating gate by ultraviolet radiation.
FIG. 1A illustrates schematically a non-volatile memory in the form of an EEPROM cell with a floating gate for storing charge. An electrically erasable and programmable read-only memory (EEPROM) has a similar structure to EPROM, but additionally provides a mechanism for adding and removing charge electrically from its floating gate upon application of proper voltages without the need for exposure to UV radiation.
An array of such EEPROM cells is referred to as a “Flash” EEPROM array when an entire array of cells, or significant group of cells of the array, is electrically erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
FIG. 1B illustrates schematically a non-volatile memory in the form of a NROM cell with a dielectric layer for storing charge. Instead of storing charge in a floating gate, it has a dielectric layer for storing charge. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers.
Cell and Array Structure
FIG. 1C illustrates schematically a flash EEPROM cell having both a select gate and a control or steering gate. Memory devices having such a cell structure are described in U.S. Pat. No. 5,313,421, which patent is incorporated herein by reference. The memory cell 10 has a “split-channel” 12 between source 14 and drain 16 diffusions. A cell is formed effectively with two transistors T1 and T2 in series. T1 serves as a memory transistor having a floating gate 20 and a control gate 30. The control gate will also be referred to as a steering gate 30. The floating gate is capable of storing a selectable amount of charge. The amount of current that can flow through the T1's portion of the channel depends on the voltage on the steering gate 30 and the amount of charge residing on the intervening floating gate 20. T2 serves as a select transistor having a select gate 40. When T2 is turned on by a voltage at the select gate 40, it allows the current in the T1's portion of the channel to pass between the source and drain.
FIG. 1D illustrates schematically another flash EEPROM cell having dual floating gates and independent select and control gates. Memory devices having such a cell structure are described in co-pending U.S. patent application Ser. No. 09/343,493, filed Jun. 30, 1999, which disclosure is incorporated herein by reference. The memory cell 10′ is similar to that of FIG. 1C except it effectively has three transistors in series. Between a pair of memory transistors, T1—left and T1—right, is a select transistor T2. The memory transistors have floating gates 20′ and 20″ and steering gates 30′ and 30″ respectively. The select transistor T2 is controlled by a control gate 40′. At any one time, only one of the pair of memory transistors is accessed for read or program. When the storage unit T1—left is being accessed, both the T2 and T1—right are turned on to allow the current in the T1—left's portion of the channel to pass between the source and the drain. Similarly, when the storage unit T1—right is being accessed, T2 and T1—left are turned on. Erase is effected by having a portion of the select gate polysilicon in close proximity to the floating gate and applying a substantial positive voltage (e.g. 20V) to the select gate so that the electrons stored within the floating gate can tunnel to the select gate polysilicon.
FIG. 2 is a schematic block diagram of an addressable array of memory cells in rows and columns with decoders. A two-dimensional array of memory cells 100 is formed, with each row of memory cells connecting by their sources and drains in a daisy-chain manner. Each memory cell 50 has a source 54, a drain 56 and a steering gate 60 and a select gate 70. The cells in a row have their select gates connected to a word line 110. The cells in a column have their sources and drains respectively connected to bit lines 124, 126. The cells in a column also have their steering gates connected by a steering line 130.
When the cell 50 is addressed for programming or reading, appropriate programming or reading voltages (VS, VD, VSTG, VSLG) must be supplied respectively to the cell's source 54 and drain 56, steering gate 60 and select gate 70. A word line decoder 112 selectively connects a selected word line to a select voltage VSLG. A bit line decoder 122 selectively connects the pair of bit lines 124, 126 in an addressed column respectively to source voltage VS and drain voltage VD. Similarly, a steering line decoder 132 selectively connects the steering line 130 in the addressed column to a steering or control gate voltage VSTG.
Thus, a specific cell of the two-dimensional array of flash EEPROM cells is addressed for programming or reading by a selection or decode in the column direction of a pair of bit lines and a steering line, and in the row direction of a word line. In order to increase performance, the column decoders 122 and 132 allow a group of columns to be selected, and therefore a corresponding group or chunk of cells to be accessed in parallel, thereby accessing the row of cells chunk-by-chunk.
Previously, many flash EEPROM devices have had a word line connecting all the control gates of cells along each row. Thus, the word line essentially performs two functions: row selection; and supplying control gate voltage to all cells in the row for reading or programming. It is often difficult to perform both of these functions in an optimum manner with a single voltage. If the voltage is sufficient for row selection, it may be higher than desirable for programming. However, with a cell having independent steering gate and select gate, the word line which is connected to the select gates of cell in a row need only perform the selection function while the steering line performs the function of supplying optimum, independent control gate voltage to individual cells in a column.
Cell Characteristics
In the usual two-state EEPROM cell, at least one current breakpoint level is established so as to partition the conduction window into two regions. When a cell is read by applying predetermined, fixed voltages, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current IREF). If the current read is higher than that of the breakpoint level or IREF, the cell is determined to be in one logical state (e.g., a “zero” state), while if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a “one” state). Thus, such a two-state cell stores one bit of digital information. A reference current source, which may be externally programmable, is often provided as part of a memory system to generate the breakpoint level current.
In order to increase memory capacity, flash EEPROM devices are being fabricated with higher and higher density as the state of the semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to determine the threshold voltage at the control gate that causes the conduction current to just “trip” or transverse a fixed reference current. Thus, the detection is performed on a threshold voltage among a partitioned threshold voltage window.
FIG. 3 illustrates the relation between the source-drain current ID and the control gate voltage VSTG for four different charges Q1–Q4 that the floating gate may be selectively storing at any one time. The four solid ID versus VSTG curves represent four possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. As an example, the threshold voltage window of a population of cells may range from 0.5V to 3.5V. Six memory states may be demarcated by partitioning the threshold window into five regions in interval of 0.5V each. For example, if a reference current, IREF of 2 μA is used as shown, then the cell programmed with Q1 may be considered to be in a memory state “1” since its curve intersects with IREF in the region of the threshold window demarcated by VSTG=0.5V and 1.0V. Similarly, Q4 is in a memory state “5”.
As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.
U.S. Pat. No. 4,357,685 discloses a method of programming a 2-state EPROM in which when a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to reach the desired state. The programming pulse train used may have increasing period or amplitude.
Prior art programming circuits simply apply programming pulses to step through the threshold window from the erased or ground state until the target state is reached. Practically, to allow for adequate resolution, each partitioned or demarcated region would require at least about five programming steps to transverse. The performance is acceptable for 2-state memory cells. However, for multi-state cells, the number of steps required increases with the number of partitions and therefore, the programming precision or resolution must be increased. For example, a 16-state cell may require on average at least 40 programming pulses to program to a target state.